1. Technical Field
The present invention generally relates to semi-conductor devices. More particularly, the present invention relates to complementary FETs.
2. Background Information
Field Effect Transistors (FETs), and in particular, CMOS (complementary metal oxide semi-conductor) FETs, have become the workhorse of integrated circuits in recent years. The principal advantage of CMOS transistors over other transistors is their much lower power dissipation. As one skilled in the art will appreciate, a CMOS device includes both an N-Channel MOSFET and P-Channel MOSFET. When the input (gate) voltage is high, the NMOS device is turned on and the PMOS device turns off; and when the input voltage is low, the PMOS device turns on and the NMOS device turns off. This is the basic mode of operation of complementary switches.
FIG. 1 depicts a cross-section of a conventional complementary Thin Film Transistor (TFT) 10. A complementary TFT is made by connecting an N-Channel TFT and P-Channel TFT. The N-Channel TFT is separated from the P-Channel TFT by a minimum distance specified by design rules to minimize interaction between the two transistors.
The complementary TFT 10 is created on a glass substrate 12. A buffer layer 14 of silicon dioxide prevents contaminants from the glass substrate from entering the active region. A layer of polycrystalline silicon ("polysilicon") is patterned into active regions 16 and 18. A layer of oxide 20 (gate insulator) separates the active regions from their respective gates 22 and 24. The implantation of an N-type impurity in active region 16 defines source/drain regions 26 and 28. A P-type impurity implanted in active region 18 defines source/drain regions 30 and 32 for the PMOS transistor. One skilled in the art will understand that the above description is merely one example of a method of making a CMOS TFT.
A second exemplary complementary FET structure is shown in FIG. 2. A complementary Heterostructure Insulated Gate Field Effect Transistor (c-HIGFET) 34 is shown in cross-section in FIG. 2. As one skilled in the art will appreciate, a c-HIGFET uses a wide bandgap semiconductor barrier layer, instead of silicon dioxide used in the CMOS device 10 of FIG. 1. The advantage of such a transistor is the high mobility of carriers, due to the reduced impurity and surface scattering.
A wide bandgap semiconductor 38 is placed over narrow bandgap semiconductor 36. As one skilled in the art will know, a "wide bandgap semiconductor" refers to a semiconductor with a bandgap of about 0.4 eV to about 6.2 eV, for example, AlGaAs. Gates 40 and 42 are separated as shown for the N-channel device and the P-channel device, respectively. An N-type impurity is implanted to create source/drain regions 44 and 46, and similarly, a P-type impurity is implanted to create source/drain regions 48 and 50. Gates 40 and 42 comprise a Schottky metal.
The complementary transistors of FIG. 1 and FIG. 2, though useful advances in the semiconductor field, have their limitations. As an initial matter, the side-by-side design occupies more space than necessary, wasting the space between the N-channel device and the P-channel device. In addition, power dissipation is quite high, posing a constraint on low power applications.